[akd4648-c] 2007/04 - 1 - general description akd4648 is an evaluation board for the AK4648, stereo codec with mic/hp/spk amplifier. the akd4648 can evaluate a/d converter and d/a converte r separately in addition to loopback mode (a/d d/a). the akd4648 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. ? ordering guide akd4648 --- evaluation board for AK4648 (cable, usb interface board for connecting with usb port, and control software are packed with this. this control software does not support windows nt.) function ? dit/dir with optical input/output ? 10pin header for digital audio interface ? 10pin header for serial control mode agnd ak4115 opt in AK4648 hvdd avdd hp opt out port1 port2 line out dvdd tvdd spk d3v mic min line in vcc regulator 10pin header dsp port3 10pin header control data port4 tvdd 3.3 v dir dit figure 1. akd4648-c block diagram * circuit diagram and pcb layout are attached at the end of this manual evaluation board rev.1 for AK4648 a kd4648-c
[akd4648-c] 2007/04 - 2 - evaluation board manual ? operation sequence (1) set up the power supply lines. (1-1) in case of us ing the regulator. (1-1-1) tvdd is supplied from the regulator. set up the jumper pins. jp22 jp23 jp reg_sel tvdd_sel state reg short set up the power supply lines. [vcc] (red) = 4.3 ~ 5.0v : typ. 4.5v for regulator and hvdd of AK4648 (regulator 3.3v output : avdd, d vdd and tvdd of the AK4648 and logic) [tvdd] (orange) = open [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground (1-1-2) tvdd is supplied from the power supply connector of ?tvdd?. set up the jumper pins. jp22 jp23 jp reg_sel tvdd_sel state reg open set up the power supply lines. [vcc] (red) = 4.3 ~ 5.0v : typ. 4.5v for regulator and hvdd of AK4648 (regulator 3.3v output : avdd and dvdd of the AK4648 and logic) [tvdd] (orange) = 1.6 ~ 3.6v : typ. 3.3v for tvdd of AK4648 (tvdd dvdd) [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground (1-2) when the regulator is not used. set up the jumper pins. jp22 jp23 jp reg_sel tvdd_sel state vcc open set up the power supply lines. [vcc] (red) = 2.6 ~ 3.6v : typ. 3.3v for avdd, dvdd and hvdd of AK4648 and logic [tvdd] (orange) = 1.6 ~ 3.6v : typ. 3.3v for tvdd of AK4648 (tvdd dvdd) [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground * each supply line should be distributed from the power supply unit. (2) set up the evaluation mode, jumper pins and dip switches. (see the followings.) (3) power on. the AK4648 and ak4115 should be reset once bringing sw1 (pdn) ?l? upon power-up.
[akd4648-c] 2007/04 - 3 - ? evaluation mode in case of AK4648 evaluation using ak4115, it is neces sary to correspond to audio interface format for AK4648 and ak4115. about AK4648?s audio interface format, refer to datasheet of AK4648. about ak4115?s audio interface format, refer to table 2 on page 11 in this manual. sampling frequency (fs) of ak4115 is 22khz or more. if the fs is slower than 22khz, please use other mode. in addition, mclk of ak4115 support s 256fs and 512fs. when evaluating it in a condition except this, please use other mode. (1) external slave mode (1-1) evaluation of a/d using dit of ak4115 (1-2) evaluation of d/a using dir of ak4115 (1-3) evaluation of loop-back using ak4115 (1-4) all interface signals are fed externally (2) external master mode (2-1) evaluation of a/d using dit of ak4115 (2-2) evaluation of d/a using dir of ak4115 (2-3) evaluation of loop-back using ak4115 (2-4) all interface signals are fed externally (3) pll slave mode (3-1) reference clock : mcki pin (3-1-1) evaluation of a/d using dit of ak4115 (3-1-2) evaluation of loop-back using ak4115 (3-1-3) all interface signals are fed externally (3-2) reference clock : bick or lrck pin (3-2-1) evaluation of a/d using dit of ak4115 (3-2-2) evaluation of d/a using dir of ak4115 (3-2-3) evaluation of loop-back using ak4115 (3-2-4) all interface signals are fed externally (4) pll master mode (4-1) evaluation of a/d using dit of ak4115 (4-2) evaluation of loop-back using ak4115 (4-3) all interface signals are fed externally
[akd4648-c] 2007/04 - 4 - (1) external slave mode (1-1) evaluation of a/d using dit of ak4115 port2 (dit) and x1 (x?tal) are used. dit generates audio bi-phase signal from received data and which is output through optical connector (totx141). nothing should be connected to port1 (dir) and port3 (dsp). the jumper pins should be set as follows. (1-2) evaluation of d/a using dir of ak4115 port1 (dir) is used. nothing should be connected to port2 (dit) and port3 (dsp). the jumper pins should be set as follows. (1-3) evaluation of loop-back using ak4115 x1 (x?tal) is used. nothing should be connected to port1 (dir) and port3 (dsp). the jumper pins should be set as follows. (1-4) all interface signals are fed externally port3 (dsp) is used. nothing should be connected to port1 (dir) and port2 (dit). the jumper pins should be set follows. jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slave jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp17 lrck jp16 bick jp15 dir_mclk jp20 sdto-in jp19 dir_sel maste r slav e jp21 sdti ad c di r
[akd4648-c] 2007/04 - 5 - (2) external master mode (2-1) evaluation of a/d using dit of ak4115 port2 (dit) and x1 (x?tal) are used. nothing should be connected to port1 (dir) and port3 (dsp). in master mode, bick and lrck of AK4648 should be input to ak4115. please refer to table2 on page 11. the jumper pins should be set as follows. (2-2) evaluation of d/a using dir of ak4115 port1 (dir) is used. nothing should be connected to port2 (dit) and port3 (dsp). in master mode, bick and lrck of AK4648 should be input to ak4115. please refer to table2 on page 11. the jumper pins should be set as follows. (2-3) evaluation of loop-back using ak4115 x1 (x?tal) is used. nothing should be connected to port1 (dir) and port3 (dsp). the jumper pins should be set as follows. (2-4) all interface signals are fed externally port3 (dsp) is used. nothing should be connected to port1 (dir) and port2 (dit). the jumper pins should be set as follows. jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slave jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp17 lrck jp16 bick jp15 dir_mclk jp20 sdto-in jp19 dir_sel maste r slav e jp21 sdti ad c di r
[akd4648-c] 2007/04 - 6 - (3) pll slave mode (3-1) reference clock : mcki pin (3-1-1) evaluation of a/d using dit of ak4115 port2 (dit) and port3 (dsp) are used. nothing should be connected to port1 (dir). the system clock (pll reference clock) should be connected to mclk of port3. mcko of AK4648 should be input to ak4115?s xti. x?tal oscillator should be removed from x1. the jumper pins should be set as follows. (3-1-2) evaluation of loop-back using ak4115 port2 (dit) and port3 (dsp) are used. nothing should be connected to port1 (dir). the system clock (pll reference clock) should be connected to mclk of port3. mcko of AK4648 should be input to ak4115?s xti. x?tal oscillator should be removed from x1. the jumper pins should be set as follows. (3-1-3) all interface signals are fed externally port3 (dsp) is used. nothing should be connected to port1 (dir) and port2 (dit). bick and lrck inputs should be synchronized with mcko of AK4648. mclk (pll reference clock), bick, lrck and sdti are supplied from port3. the jp14 (4115_mcki)?s lower side (mcko of AK4648) should be connected to mclk of dsp. the jumper pins should be set as follows. jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp20 sdto_in jp2 rin3 vcoc jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp20 sdto_in jp2 rin3 vcoc jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp20 sdto_in jp2 rin3 vcoc
[akd4648-c] 2007/04 - 7 - (3-2) reference clock : bick or lrck pin (3-2-1) evaluation of a/d using dit of ak4115 x1 (x?tal) and port2 (dit) are used. nothing should be connected to port1 (dir). the jumper pins should be set as follows. (3-2-2) evaluation of d/a using dir of ak4115 port1 (dir) is used. nothing should be connected to port2 (dit) and port3 (dsp). the jumper pins should be set as follows. (3-2-3) evaluation of loop-back using ak4115 x1 (x?tal) is used. nothing should be connect ed to port1 (dir), port2 (dit), and port3 (dsp). the jumper pins should be set as follows. jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp20 sdto_in jp2 rin3 vcoc jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp20 sdto_in jp2 rin3 vcoc jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp20 sdto_in jp2 rin3 vcoc
[akd4648-c] 2007/04 - 8 - (3-2-4) all interface signals are fed externally port3 (dsp) is used. nothing should be connected to port1 (dir) and port2 (dit). bick, lrck, and sdti are supplied from port3. the jumper pins should be set as follows. (4) pll master mode (4-1) evaluation of a/d using dit of ak4115 port2 (dit) and port3 (dsp) are used. nothing should be connected to port1(dir). the system clock (pll reference clock) should be connected to mclk of port3. in case of supplying mcko to dsp, the jp14 (4115_mcki)?s lower side should be connected to mclk of dsp. x?tal oscillator should be removed from x1. in master mode, bick and lrck of AK4648 should be input to ak4115. please refer to table2 on page 11. the jumper pins should be set as follows. (4-2) evaluation of loop-back port2 (dit) and port3 (dsp) are used. nothing should be connected to port1(dir). the system clock (pll reference clock) should be connected to mclk of port3. in case of supplying mcko to dsp, the jp14 (4115_mcki)?s lower side should be connected to mclk of dsp. x?tal oscillator should be removed from x1. the jumper pins should be set as follows. jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp20 sdto_in jp2 rin3 vcoc jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp20 sdto_in jp2 rin3 vcoc jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp20 sdto_in jp2 rin3 vcoc
[akd4648-c] 2007/04 - 9 - (4-3) all interface signals are fed externally port3 (dsp) is used. nothing should be connected to port1 (dir) and port2 (dit). the system clock (pll reference clock) should be connected to mclk of port3. in case of supplying mcko to dsp, the jp14 (4115_mcki)?s lower side should be connected to mclk of dsp. x?tal oscillator should be removed from x1. the jumper pins should be set as the follows. jp17 lrck jp16 bick jp15 dir_mclk jp14 4115_mcki jp19 dir_sel maste r slav e jp21 sdti ad c di r jp20 sdto_in jp2 rin3 vcoc
[akd4648-c] 2007/04 - 10 - ? dip switch set up [s1] (sw dip1-4): mode setting for AK4648 and ak4115. no. name on (?h?) off (?l?) default 1 cad0 AK4648 chip address setting: (see table 4) off 2 ocks1 ak4115 master clock setting: (see table 3) off 3 dif0 off 4 dif1 ak4115 audio format setting see table 2 off table 1. mode setting for AK4648 and ak4115 lrck bick mode dif1 dif0 daux sdto i/o i/o 1 0 0 24bit, left justified 24bit, left justified h/l o 64fs o 2 0 1 24bit, i 2 s 24bit, i 2 s l/h o 64fs o 3 1 0 24bit, left justified 24bit, left justified h/l i 64-128fs i 4 1 1 24bit, i 2 s 24bit, i 2 s l/h i 64-128fs i table 2. setting for ak4115 audio interface format mode ocks1 mcko1 pin x?tal 0 0 256fs 256fs 1 1 512fs 512fs table 3. setting for ak4115 master clock
[akd4648-c] 2007/04 - 11 - ? other jumper pins set up [jp1] (gnd) : analog ground and digital ground. short : common. (the connector ?dgnd? can be open.) open : separated. [jp2] : selection of rin3 path or pll mode. rin3 : rin3 path. vcoc : pll mode. [jp4] (lin1) : selection of using mic-power supply for lin1. short : mic-power is supplied. open : mic-power is not supplied. [jp7] (rin1) : selection of using mic-power supply for rin1. short : mic-power is supplied. open : mic-power is not supplied. [jp8] (lin2) : selection of using mic-power supply for lin2. short : mic-power is supplied. open : mic-power is not supplied. [jp9] (rin2) : selection of using mic-power supply for rin2. short : mic-power is supplied. open : mic-power is not supplied. [jp12] : selection of lin3 path or min path. short : lin3 path. open: min path. [jp14] (4114_mcki) : ak4115 clock source. open : x?tal of ak4115 is used. short : mcko of AK4648 (x?tal oscillator should be removed from x1). [jp18] (signal v_select) : selection of power supply for logic(u4). d3v : it is supplied from d3v. tvdd : it is supplied from tvdd. [jp20] (sdto_in) : sdto of port3. short : it supply sdto to port3. open : it does not supply sdto to port3.
[akd4648-c] 2007/04 - 12 - ? the function of the toggle sw [sw1] (pdn): power down of AK4648. keep ?h? during normal operation. [sw2] (dir): power down of ak4115. keep ?h? during normal operation. keep ?l? when ak4115 is not used. *upper-side is ?h? and lower-side is ?l?. ? indication for led [led1] (erf): monitor int0 pin for the ak4115. led turns on when some erro r has occurred to ak4115. ? serial control the akd4648-c can be connected via the usb port with attached usb interface board. connect port4 (ctrl) with pc by 10 wire flat cable packed with the akd4648-c. table 4 shows switch and jumper settings for serial control. note) when i 2 c-bus is controlled by p via port4, resistor value of r100 should be properly selected. connect scl sda 10pin header 10pin connector 10 wire flat cable for pc akd4648-c usb i/f board usb cable port4 1 10 5 6 figure 2. connect of 10 wire flat cable s1 mode cad0 cad0=0 off default i2c cad0=1 on table 2. serial control setting
[akd4648-c] 2007/04 - 13 - ? analog input/output circuits (1) input circuits input circuits of lin1/rin1, lin2/rin 2, lin3/rin3, lin4/rin4, and min. jp9 rin2 + c20 1u r13 2.2k jp4 lin1 6 4 3 j3 lin2/rin2 + c15 1u 6 4 3 j1 lin1/rin1 r12 2.2k jp7 rin1 + c13 1u + c19 1u lin1 rin2 lin2 mpwr rin1 jp8 lin2 r17 2.2k r16 2.2k jp12 lin3 + c21 1u + c22 1u 6 4 3 j5 min/lin3/rin3 r18 20k min/lin3 rin3 + c23 1u + c25 1u 6 4 3 j8 lin4/rin4 lin4 rin4 figure 3. input circuits lin1/rin1, lin2/rin2, lin3/rin3, lin4/rin4, and min
[akd4648-c] 2007/04 - 14 - when lin3/rin3 paths of AK4648 are used, jp2 and jp12 should be set as follows. ain3 bit = ?1? (register address 21h) when min path of AK4648 is used, jp12 should be set as follows. ain3 bit = ?1? (register address 21h) when mic- power output (mpwr pin) of AK4648 is used, jp4 (lin1) / jp7 (rin1) and / or jp8 (lin2) / jp9 (rin2) should be short. jp12 lin3 jp2 rin3 vcoc jp12 lin3
[akd4648-c] 2007/04 - 15 - (2) output circuits (2-1) hp output circuit c18 0.22u r11 short hvcm r15 10 r10 short + c14 220u c17 0.22u + c16 220u 6 4 3 j2 hp r14 10 hpr hpl jp5 hpl cap-less jp3 hpr cap-less hvcm gnd jp6 figure 4. hp output circuit (2-1-1) single-ended mode the jumper pins should be set as follows. (2-1-2) pseudo cap-less mode the jumper pins should be set as follows. jp3 hpr cap-less jp6 hvcm gnd jp5 hpl cap-less jp3 hpr cap-less jp6 hvcm gnd jp5 hpl cap-less
[akd4648-c] 2007/04 - 16 - (2-2) lout/rout output circuit r19 open + c24 1u + c26 1u 6 4 3 j7 lout/rout lout rout jp13 lineout figure 5. lout/rout output circuit the jumper pins should be set as follows. jp13 lineout
[akd4648-c] 2007/04 - 17 - (2-3) spk output circuit 6 4 3 j6 spk/ r sprp sprn jp10 high spn jp11 high spp 6 4 3 j4 spk/ l spln splp 1 tp1 splp 1 tp2 spln 1 tp3 sprp 1 tp4 sprn figure 6. spk output circuit (2-3-1) stereo spk mode the jumper pins should be set as follows. (2-3-2) mono spk mode the jumper pins should be set as follows. (2-3-3) high power spk mode the jumper pins should be set as follows. ? akm assumes no responsibility for the trouble when using the above circuit examples. jp10 high spn jp11 high spp jp10 high spn jp11 high spp jp10 high spn jp11 high spp
[akd4648-c] 2007/04 - 18 - control software manual ? set-up of evaluation board and control software 1. set up the akd4648-c according to previous term. 2. connect ibm-at compatible pc with akd4648-c by 10-line type flat cable via the usb port with attached usb interface board (packed with akd4648-c). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of control software driver by akm device control software?. in case of windows95/98/me, this installation is not needed. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?akd4648-c evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?akd4648.exe? to set up the control program. 5. then please evaluate according to the follows. ? operation flow keep the following flow. 1. set up the control program according to explanation above. 2. click ?port reset? button. ? explanation of each buttons [port reset] : set up the usb interface board (akdusbif-a) . [write default] : initialize the register of AK4648. [all write] : write all registers that is currently displayed. [function1] : dialog to write data by keyboard operation. [function2] : dialog to write data by keyboard operation. [function3] : the sequence of register setting can be set and executed. [function4] : the sequence that is created on [function3] can be assigned to buttons and executed. [function5]: the register setting that is created by [save] function on main window can be assigned to buttons and executed. [save] : save the current register setting. [open] : write the saved values to all register. [write] : dialog to write data by mouse operation. [filter] : set programmable filter (fil1, fil3, eq) of AK4648. [5 band eq] : set 5-band equalizer of AK4648. ? indication of data input data is indicated on the register map. red letter indicates ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet.
[akd4648-c] 2007/04 - 19 - ? explanation of each dialog 1. [write dialog] : dialog to write data by mouse operation there are dialogs corresponding to each register. click the [write] button corresponding to each register to set up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. if you want to write the input data to AK4648, click [ok] button. if not, click [cancel] button. 2. [function1 dialog] : dialog to write data by keyboard operation address box: input registers address in 2 figures of hexadecimal. data box: input registers data in 2 figures of hexadecimal. if you want to write the input data to AK4648, click [ok] button. if not, click [cancel] button. 3. [function2 dialog] : dialog to evaluate ivol and dvol address box: input registers address in 2 figures of hexadecimal. start data box: input starts data in 2 figures of hexadecimal. end data box: input end data in 2 figures of hexadecimal. interval box: data is written to AK4648 by this interval. step box: data changes by this step. mode select box: if you check this check box, data reaches end data, and returns to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 if you do not check this check box, data reaches end data, but does not return to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 if you want to write the input data to AK4648, click [ok] button. if not, click [cancel] button.
[akd4648-c] 2007/04 - 20 - 4. [save] and [open] 4-1. [save] save the current register setting data. the extension of file name is ?akr?. (operation flow) (1) click [save] button. (2) set the file name and push [save] button. the extension of file name is ?akr?. 4-2. [open] the register setting data saved by [save] is written to AK4648. the file type is the same as [save]. (operation flow) (1) click [open] button. (2) select the file (*.akr) and click [open] button.
[akd4648-c] 2007/04 - 21 - 5. [function3 dialog] the sequence of register setting can be set and executed. (1) click [f3] button. (2) set the cont rol sequence. set the address, data and interval time. set ?-1? to the address of the step where the sequence should be paused. (3) click [start] button. then this sequence is executed. the sequence is paused at the step of interval="-1". click [start] button, the sequence restarts from the paused step. this sequence can be saved and opened by [save] and [open] button on the function3 window. the extension of file name is ?aks?. figure 7. window of [f3]
[akd4648-c] 2007/04 - 22 - 6. [function4 dialog] the sequence that is created on [function3] can be assigned to buttons and executed. when [f4] button is clicked, the window as shown in figure 8 opens. figure 8. [f4] window
[akd4648-c] 2007/04 - 23 - 6-1. [open] buttons on left side and [start] buttons (1) click [open] button and select the sequence file (*.aks). the sequence file name is displayed as shown in figure 9. figure 9. [f4] window(2) (2) click [start] button, then the sequence is executed. 3-2. [save] and [open] buttons on right side [save] : the sequence file names can assign be saved. the file name is *.ak4. [open] : the sequence file names assign that are saved in *.ak4 are loaded. 3-3. note (1) this function doesn't support the pause function of sequence function. (2) all files need to be in same folder used by [save] and [open] function on right side. (3) when the sequence is changed in [function3], the file should be loaded again in order to reflect the change.
[akd4648-c] 2007/04 - 24 - 7. [function5 dialog] the register setting that is created by [save] function on main window can be assigned to buttons and executed. when [f5] button is clicked, the following window as shown in figure 10 opens. figure 10. [f5] window 7-1. [open] buttons on left side and [write] button ( 1) click [open] button and select the register setting file (*.akr). the register setting file name is displayed as shown in figure 11. (2) click [write] button, then the register setting is executed.
[akd4648-c] 2007/04 - 25 - figure 11. [f5] windows(2) 7-2. [save] and [open] buttons on right side [save] : the register setting file names assign can be saved. the file name is *.ak5 . [open] : the register setting file names assign that are saved in *.ak5 are loaded. 7-3. note (1) all files need to be in same folder used by [save] and [open] function on right side. (2) when the register setting is changed by [save] button in main window, the file should be loaded again in order to reflect the change.
[akd4648-c] 2007/04 - 26 - 8. [filter dialog] this dialog can easily set the AK4648?s programmable filter. figure 12. [filter] window 8-1. value input columns on left side [sampling rate] ? input value of sampling frequency [unit : hz] [cut off frequency of fil1] ? input value of cut off frequency of fil1 [unit : hz] [cut off frequency of fil3] ? input value of cut off frequency of fil3 [unit : hz] [pole frequency of eq] ? input value of pole frequency of eq [unit : hz] [zero frequency of eq] ? input value of zero frequency of eq [unit : hz] [fil3 gain] ? input value of gain of fil3 (0~ ? 10db) [unit : db] [eq gain] ? input value of gain of eq (+12~0db) [unit : db] 8-2. check box on left side check box check check off fil1 fil1 bit =?1? fil1 bit =?0? fil3 fil3 bit =?1? fil3 bit =?0? eq eq bit =?1? eq bit =?0? lpf of fil1 f1as bit =?1?(lpf) f1as bit =?0?(hpf) lpf of fil3 f3as bit =?1?(lpf) f3as bit =?0?(hpf) 8-2. [register setting] panel and [register setting] button on right side click [register setting] button, then filter coefficient set by 8-1 and 8-2 is written on [register setting] panel. (it is also written to the actual control register of the AK4648.)
[akd4648-c] 2007/04 - 27 - 9. [5 band eq dialog] this dialog can easily set the AK4648?s 5-band equalizer. figure 13. [5 band eq] window when the check box of ?5 band eq? is checked, 5-band equalizer is on (fbeq bit = ?1?). when the slide button is changed, its value is written to the internal register immediately.
[akd4648-c] 2007/04 - 28 - measurement results [measurement condition] measurement unit: audio precision, system two cascade dual domain ext slave mode bick: 64fs bit: 16bit measurement frequency: <10hz 20khz (adc) <10hz 22khz (dac) power supply: avdd=dvdd=tvdd=3.3v, hvdd=4.5v temperature: room input frequency: 1khz sampling frequency: 44.1khz
[akd4648-c] 2007/04 - 29 - 1. table data adc (lin2/rin2) characteristics (i vol=0db, alc = off, lin2/rin2 ? adc ? ivol) parameter lch [db] rch [db] mic-amp gain 0db +20db 0db +20db s/(n+d) 20khzlpf ( ? 1db) 88.6 83.2 88.5 83.2 d-range 20khzlpf + a-weighted 95.2 86.5 95.2 86.5 s/n 20khzlpf + a-weighted 95.3 86.5 95.3 86.5 dac (lout/rout) characteristics (dac ? lout/rout) parameter lch [db] rch [db] s/(n+d) 20khzlpf ( ? 3db) 87.5 87.4 s/n a-weighted 92.3 92.3 dac (hp(single-ended mode)) characteristics (dac-->hp(single-ended mode)), r l =16 ? parameter lch [db] rch [db] s/(n+d) 20khzlpf ( ? 3db) (hpg=0db) 69.4 69.5 s/n a-weighted 91.1 91.1 dac (hp(pseudo cap-less mode)) characteris tics (dac-->hp(pseudo cap-less mode)), r l =16 ? parameter lch [db] rch [db] s/(n+d) 20khzlpf ( ? 3db) (hpg=0db) 64.7 65.0 s/n a-weighted 90.1 90.1 dac (sp(stereo)) characteri stics (dac-->sp(stereo)), r l =8 ? parameter lch [db] rch [db] s/(n+d) 20khzlpf (-0.5dbfs) (spkg2-0:+4.43db) 61.5 61.6 s/n a-weighted 90.4 90.3 dac (sp(high power mode)) characteristics (dac-->sp(high power mode)), r l =8 ? parameter [db] s/(n+d) 20khzlpf (-0.5dbfs) (spkg2-0:+4.43db) 61.5 s/n a-weighted 91.4
[akd4648-c] 2007/04 - 30 - 2. plot data 2-1 adc (lin2/rin2 ? adc)(mic-amp gain:+20db) AK4648 lin2/rin2 => adc (mgain+20db) thd + n vs input level, fs=44.1khz, fin=1khz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr -100 -60 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 d b f s figure 14. thd+n vs. input level AK4648 lin2/rin2 => adc (mgain+20db) thd + n vs input frequency, fs=44.1khz, -1db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -60 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 d b f s figure 15. thd+n vs. input frequency
[akd4648-c] 2007/04 - 31 - AK4648 lin2/rin2 => adc (mgain+20db) linearity, fs=44.1khz, fin=1khz -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr -100 +0 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b f s figure 16. linearity AK4648 lin2/rin2 => adc (mgain+20db) frequency response, fs=44.1khz, -1db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -3 +0 -2.8 -2.6 -2.4 -2.2 -2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 d b f s figure 17. frequency response
[akd4648-c] 2007/04 - 32 - AK4648 lin2/rin2 => adc (mgain+20db) fft fs=44.1khz, -1db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 18. fft plot (input level= -1dbfs) AK4648 lin2/rin2 => adc (mgain+20db) fft fs=44.1khz, -60db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 19. fft plot (input level= -60dbfs)
[akd4648-c] 2007/04 - 33 - AK4648 lin2/rin2 => adc (mgain+20db) fft fs=44.1khz, no signal 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 20. fft plot (no signal) AK4648 lin2/rin2=>adc (mgain+20db) crosstalk, fs=44.1khz, -1db input, red r=>l, blue l=>r 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 -70 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 d b 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 figure 21. crosstalk plot
[akd4648-c] 2007/04 - 34 - 2-2 adc (lin2/rin2 ? adc)(mic-amp gain:0db) AK4648 lin2/rin2 => adc (mgain 0db) thd + n vs input level , fs=44.1khz, fin=1khz -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr -100 -60 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 d b f s figure 22. thd+n vs. input level AK4648 lin2/rin2 => adc (mgain 0db) thd + n vs input frequency, fs=44.1khz, -1db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -60 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 d b f s figure 23. thd+n vs. input frequency
[akd4648-c] 2007/04 - 35 - AK4648 lin2/rin2 => adc (mgain 0db) linearity, fs=44.1khz, fin=1khz -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr -100 +0 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b f s figure 24. linearity AK4648 lin2/rin2 => adc (mgain 0db) frequency response, fs=44.1khz, -1db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -3 +0 -2.8 -2.6 -2.4 -2.2 -2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 d b f s figure 25. frequency response
[akd4648-c] 2007/04 - 36 - AK4648 lin2/rin2 => adc (mgain 0db) fft fs=44.1khz, -1db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 26. fft plot (input level= -1dbfs) AK4648 lin2/rin2 => adc (mgain 0db) fft fs=44.1khz, -60db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 27. fft plot (input level = -60dbfs)
[akd4648-c] 2007/04 - 37 - AK4648 lin2/rin2 => adc (mgain 0db) fft fs=44.1khz, no signal 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 28. fft plot ( no signal ) AK4648 lin2/rin2 => adc (mgain 0db) crosstalk, fs=44.1khz, -1db input, red r=>l, blue l=>r 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 -70 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 d b 5 5 5 5 5 figure 29. crosstalk plot
[akd4648-c] 2007/04 - 38 - 2-3 dac (dac ? lout/rout) AK4648 dac => lineout thd + n vs input level , fs=44.1khz, fin=1khz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -100 -40 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b r a figure 30. thd+n vs. input level AK4648 dac => lineout thd + n vs input frequency, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -40 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b r a figure 31. thd+n vs. input frequency
[akd4648-c] 2007/04 - 39 - AK4648 dac => lineout linearity, fs=44.1khz, fin=1khz -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -100 +0 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b r a figure 32. linearity AK4648 dac => lineout frequency response, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -2 +1 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 +0 +0.2 +0.4 +0.6 +0.8 d b r a figure 33. frequency response
[akd4648-c] 2007/04 - 40 - AK4648 dac => lineout fft, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 34. fft plot (input level= 0dbfs) AK4648 dac => lineout fft, fs=44.1khz, -60db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 35. fft plot (input level = -60dbfs)
[akd4648-c] 2007/04 - 41 - AK4648 dac => lineout fft, fs=44.1khz, no signal 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 36. fft plot (no signal) AK4648 dac => lineout crosstalk, fs=44.1khz, 0db input, red r=>l, blue l=>r 20 20k 50 100 200 500 1k 2k 5k 10k hz -120 -80 -118 -116 -114 -112 -110 -108 -106 -104 -102 -100 -98 -96 -94 -92 -90 -88 -86 -84 -82 d b 5 5 5 5 5 5 5 5 5 figure 37. crosstalk plot
[akd4648-c] 2007/04 - 42 - 2-4 dac (dac ? hp(single-ended mode))(hpg=0db) AK4648 dac =>hp (single-end) thd + n vs input level , fs=44.1khz, fin=1khz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -100 -40 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b r a figure 38. thd+n vs. input level AK4648 dac =>hp (single-end) thd + n vs input frequency, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -40 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b r a figure 39. thd+n vs. input frequency
[akd4648-c] 2007/04 - 43 - AK4648 dac => hp (single-end) linearity, fs=44.1khz, fin=1khz -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -100 +0 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b r a 5 figure 40. linearity AK4648 dac => hp (single-end) frequency response, fs=44.1khz, 0db input 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k hz -2 +1 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 +0 +0.2 +0.4 +0.6 +0.8 d b r a figure 41. frequency response
[akd4648-c] 2007/04 - 44 - AK4648 dac =>hp (single-end) fft, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 42. fft plot (input level= 0dbfs) AK4648 dac => hp (single-end) fft, fs=44.1khz, -60db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 43. fft plot (input level = -60dbfs)
[akd4648-c] 2007/04 - 45 - AK4648 dac => hp (single-end) fft, fs=44.1khz, no signal 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 44. fft plot (no signal) AK4648 dac =>hp (single-end) crosstalk, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -120 -40 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b figure 45. crosstalk plot
[akd4648-c] 2007/04 - 46 - 2-5 dac (dac ? hp(pseudo cap-less mode))(hpg=0db) AK4648 dac =>hp (pseudo cap-less) thd + n vs input level, fs=44.1khz, fin=1khz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -100 -40 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b r a figure 46. thd+n vs. input level
[akd4648-c] 2007/04 - 47 - AK4648 dac =>hp (pseudo cap-less) thd + n vs input frequencyl, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -40 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b r a figure 47. thd+n vs. input frequency (non invert signal input) AK4648 dac => hp (pseudo cap-less) thd + n vs input frequency, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -40 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b r a figure 48. thd+n vs. input frequency (invert signal input)
[akd4648-c] 2007/04 - 48 - AK4648 dac => hp (pseudo cap-less) linearity, fs=44.1khz, fin=1khz -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -100 +0 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b r a 5 figure 49. linearity AK4648 dac => hp (pseudo cap-less) frequency response, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -1.8 +1 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 +0 +0.2 +0.4 +0.6 +0.8 d b r a figure 50. frequency response
[akd4648-c] 2007/04 - 49 - AK4648 dac =>hp (pseudo cap-less) fft, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 51. fft plot (input level= 0dbfs) AK4648 dac => hp (pseudo cap-less) fft, fs=44.1khz, -60db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 52. fft plot (input level = -60dbfs)
[akd4648-c] 2007/04 - 50 - AK4648 dac => hp (pseudo cap-less) fft, fs=44.1khz, no signal 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 53. fft plot (no signal) AK4648 dac=>hp (pseudo cap-less) crosstalk, fs=44.1khz, 0db input, red r=>l, blue l=>r 20 20k 50 100 200 500 1k 2k 5k 10k hz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b figure 54. crosstalk plot
[akd4648-c] 2007/04 - 51 - 2-6 dac (dac-->sp(stereo))(spkg2-0:+4.43db) AK4648 dac =>spk (stereo) thd + n vs input level, fs=44.1khz, fin=1khz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -100 -40 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b r a figure 55. thd+n vs. input level AK4648 dac =>spk (stereo) thd + n vs input frequency, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -40 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b r a figure 56. thd+n vs. input frequency
[akd4648-c] 2007/04 - 52 - AK4648 dac =>spk (stereo) linearity, fs=44.1khz,fin=1khz -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -100 +0 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b r a figure 57. linearity AK4648 dac =>spk (stereo) frequency response, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -2 +1 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 +0 +0.2 +0.4 +0.6 +0.8 d b r a figure 58. frequency response
[akd4648-c] 2007/04 - 53 - AK4648 dac =>spk (stereo) fft, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 59. fft plot (input level= 0dbfs) AK4648 dac =>spk (stereo) fft, fs=44.1khz, -60db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 60. fft plot (input level = -60dbfs)
[akd4648-c] 2007/04 - 54 - AK4648 dac =>spk (stereo) fft, fs=44.1khz, no signal 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 61. fft plot (no signal) AK4648 dac =>spk (stereo) crosstalk, fs=44.1khz, 0db input, red r=>l, blue l=>r 20 20k 50 100 200 500 1k 2k 5k 10k hz -120 -70 -117.5 -115 -112.5 -110 -107.5 -105 -102.5 -100 -97.5 -95 -92.5 -90 -87.5 -85 -82.5 -80 -77.5 -75 -72.5 d b 5 5 5 5 5 figure 62. crosstalk plot
[akd4648-c] 2007/04 - 55 - AK4648 dac =>spk (stereo) level (w) vs amplitude lch green, rch yellow, thd + n vs amplitude lch red, rch blue 0 1.2 100m 200m 300m 400m 500m 600m 700m 800m .9 1 1.1 w -60 +0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 dbfs -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b figure 63. thd+n & output power vs. input level (spkg=+12.65db)
[akd4648-c] 2007/04 - 56 - 2-7 dac (dac-->sp(high power mode))(spkg2-0:+4.43db) AK4648 dac =>spk (high power) thd + n vs input level, fs=44.1khz, fin=1khz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -100 -40 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b r a figure 66. thd+n vs. input level AK4648 dac =>spk (high power) thd + n vs input frequency, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -40 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 d b r a figure 67. thd+n vs. input frequency
[akd4648-c] 2007/04 - 57 - AK4648 dac =>spk (high power) linearity, fs=44.1khz, fin=1khz -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -100 +0 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 d b r a figure 68. linearity AK4648 dac =>spk (high power) frequency response, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -2 +1 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 +0 +0.2 +0.4 +0.6 +0.8 d b r a figure 69. frequency response
[akd4648-c] 2007/04 - 58 - AK4648 dac =>spk (high power) fft, fs=44.1khz, 0db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 70. fft plot (input level= 0dbfs) AK4648 dac =>spk (high power) fft, fs=44.1khz, -60db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 71. fft plot (input level = -60dbfs)
[akd4648-c] 2007/04 - 59 - AK4648 dac =>spk (high power) fft, fs=44.1khz, no signal 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 72. fft plot (no signal) AK4648 dac =>spk (high power) level (w) vs amplitude green thd + n vs amplitude red 0 1.2 100m 200m 300m 400m 500m 600m 700m 800m .9 1 1.1 w -60 +0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 dbfs -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b figure 73. thd+n & output power vs. input level (spkg=+12.65db)
[akd4648-c] 2007/04 - 60 - date (yy/mm/dd) manual revision board revision reason contents 07/03/19 km088700 0 first edition 07/04/13 km088701 1 parts change AK4648 rev.a rev.b important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei emd corporation (emd) sales office or authorized distributor concerning their current status. ? emd assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? emd products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and emd assumes no responsibility relating to any such use, except with the express written consent of the representative director of emd. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an emd product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold emd harmless from any and all claims arising from the use of said product in the absence of such notification. revision history
5 5 4 4 3 3 2 2 1 1 d d c c b b a a lin1 hvdd sda mcki scl sprp mcko cad0 sprn lin4 hpr hpl dvdd pdn sdti lrck bick sdto rin4 rin1 avdd min/lin3 rin3 lin2 rin2 lout rout tvdd splp spln hvcm mpwr title size document number rev date: sheet of AK4648 1 akd4648-c b 15 friday, march 30, 2007 title size document number rev date: sheet of AK4648 1 akd4648-c b 15 friday, march 30, 2007 title size document number rev date: sheet of AK4648 1 akd4648-c b 15 friday, march 30, 2007 rin3 vcoc agnd agnd agnd agnd agnd agnd dgnd agnd + c8 10u + c8 10u r8 51 r8 51 r1 10k r1 10k nc a1 hvdd a2 sprp a4 rout/lon a5 lin4/in4+ a6 test a7 spln b1 splp b2 vss2 b3 sprn b4 lout/lop b5 rin2/in2- b6 vcom b7 vss2 c1 hvcm c2 rin4/in4- c4 lin2/in2+ c5 lin3/min c6 avdd c7 mutet d1 hpr d2 hpl d3 vss1 d6 lin1/in1- d7 vss3 e1 pdn e2 dvdd e3 rin3/vcoc e6 mpwr e7 mcki f1 tvdd f2 sdto f3 sda f4 rin1/in1+ f5 scl f6 cad0 f7 nc g1 tvdd g2 mcko g3 bick g4 lrck g5 sdti g6 nc g7 nc d4 nc d5 nc e4 nc e5 u1 AK4648 u1 AK4648 r9 51 r9 51 c5 0.1u c5 0.1u + c6 1u + c6 1u c9 0.1u c9 0.1u + c10 2.2u + c10 2.2u r6 51 r6 51 r5 51 r5 51 r2 51 r2 51 jp2 jp2 r3 51 r3 51 r4 51 r4 51 r7 51 r7 51 jp1 gnd jp1 gnd c2 0.1u c2 0.1u c12 0.1u c12 0.1u c3 4.7n c3 4.7n + c11 10u + c11 10u + c1 10u + c1 10u c7 0.1u c7 0.1u + c4 10u + c4 10u
a a b b c c d d e e e e d d c c b b a a lin1 lin2 rin2 rin1 lout rout lin4 hpl hpr mpwr rin4 min/lin3 rin3 hvcm splp spln sprp sprn title size document number rev date: sheet of input/output 1 akd4648-c a3 25 friday, march 30, 2007 title size document number rev date: sheet of input/output 1 akd4648-c a3 25 friday, march 30, 2007 title size document number rev date: sheet of input/output 1 akd4648-c a3 25 friday, march 30, 2007 gnd hvcm jp5 hpl cap-less jp5 hpl cap-less jp8 lin2 jp8 lin2 jp4 lin1 jp4 lin1 r18 20k r18 20k 6 4 3 j4 spk/l j4 spk/l jp10 high spn jp10 high spn + c22 1u + c22 1u r19 open r19 open r13 2.2k r13 2.2k 6 4 3 j2 hp j2 hp jp11 high spp jp11 high spp + c21 1u + c21 1u r16 2.2k r16 2.2k + c16 220u + c16 220u 6 4 3 j5 min/lin3/rin3 j5 min/lin3/rin3 + c24 1u + c24 1u r17 2.2k r17 2.2k 1 tp2 spln tp2 spln jp13 lineout jp13 lineout jp12 lin3 jp12 lin3 jp6 jp6 r11 short r11 short 6 4 3 j8 lin4/rin4 j8 lin4/rin4 jp9 rin2 jp9 rin2 1 tp1 splp tp1 splp + c25 1u + c25 1u + c19 1u + c19 1u + c23 1u + c23 1u c17 0.22u c17 0.22u 6 4 3 j7 lout/rout j7 lout/rout c18 0.22u c18 0.22u r14 10 r14 10 + c14 220u + c14 220u 1 tp4 sprn tp4 sprn + c20 1u + c20 1u + c13 1u + c13 1u jp7 rin1 jp7 rin1 r10 short r10 short jp3 hpr cap-less jp3 hpr cap-less 6 4 3 j1 lin1/rin1 j1 lin1/rin1 6 4 3 j6 spk/r j6 spk/r + c26 1u + c26 1u r15 10 r15 10 r12 2.2k r12 2.2k + c15 1u + c15 1u 6 4 3 j3 lin2/rin2 j3 lin2/rin2 1 tp3 sprp tp3 sprp
a a b b c c d d e e e e d d c c b b a a d3v 4115_pdn sdto dir_sdto dir_bick dir_lrck dir_mclk d3v d3v cad0 mcko tvdd d3v int0 title size document number rev date: sheet of dir/dit 1 akd4648-c a2 35 friday, march 30, 2007 title size document number rev date: sheet of dir/dit 1 akd4648-c a2 35 friday, march 30, 2007 title size document number rev date: sheet of dir/dit 1 akd4648-c a2 35 friday, march 30, 2007 h l cad0 dif1 dif0 ocks1 r20 470 r20 470 c40 5p c40 5p 1 2 3 4 8 7 6 5 s1 sw dip-4 s1 sw dip-4 4 3 2 1 rp1 47k rp1 47k r21 10k r21 10k + c28 10u + c28 10u c27 0.1u c27 0.1u 1 2 x1 11.2896mhz x1 11.2896mhz jp14 4115_mcki jp14 4115_mcki + c29 10u + c29 10u + c37 10u + c37 10u c36 0.1u c36 0.1u c35 0.1u c35 0.1u gnd 1 vcc 2 in 3 port2 totx141 port2 totx141 out 1 vcc 3 gnd 2 port1 torx141 port1 torx141 c39 0.1u c39 0.1u r22 5.1 r22 5.1 + c31 10u + c31 10u c38 0.1u c38 0.1u c30 0.1u c30 0.1u c41 0.1u c41 0.1u c42 5p c42 5p + c43 10u + c43 10u 1 2 l1 47u l1 47u dif0/rx5 1 test 2 dif1/rx6 3 xsel/rx7 5 dvdd 6 vin 7 daux 8 dvss 9 mcko1 10 mcko2 11 ovdd 12 ovss 13 bick 14 sdto 15 lrck 16 b 17 c 18 u 19 vout 20 tvdd 21 tx0 22 txp1 23 txn1 24 tvss 25 xti1 26 xto1 27 xti2 28 xto2 29 ovdd 30 ovss 31 ebick 32 emck 33 elrck 34 int0 35 int1 36 cm0/cdto/cad1 37 cm1/cdti/sda 38 ocks1/cclk/scl 39 ocks0/csn/cad0 40 dvss 42 bvss 43 ips1/iic 44 psel 45 xtl0 46 xtl1 47 filt 48 avss 49 r 50 vcom 51 avdd 52 p/sn 53 acks 54 rxn0 55 rxp0 56 avss 57 rx1 58 avdd 59 rx2 60 avss 61 rx3 62 avdd 63 ips0/rx4 64 pdn 4 dvdd 41 u2 ak4115 u2 ak4115 + c32 4.7u + c32 4.7u c34 0.1u c34 0.1u c33 0.1u c33 0.1u c44 0.1u c44 0.1u
a a b b c c d d e e e e d d c c b b a a 4115_pdn d3v tvdd pdn scl sda sdti d3v mcki tvdd avc bick tvdd lrck d3v avc dir_sdto sdto dir_lrck dir_bick dir_mclk d3v d3v int0 avc title size document number rev date: sheet of logic 1 akd4648-c a3 45 friday, march 30, 2007 title size document number rev date: sheet of logic 1 akd4648-c a3 45 friday, march 30, 2007 title size document number rev date: sheet of logic 1 akd4648-c a3 45 friday, march 30, 2007 h l nc nc sdto master slave d3v gnd tvdd vcc scl sda bick gnd sdti mclk lrck dir adc 6 5 4 3 2 1 rp3 47k rp3 47k a1 3 a2 4 a3 5 a4 6 a5 7 a6 8 a7 9 a8 10 b1 21 b2 20 b3 19 b4 18 b5 17 b6 16 b7 15 b8 14 gnd 11 gnd 12 gnd 13 vcca 1 dir 2 vccb 24 vccb 23 oe 22 u3 74avc8t245 u3 74avc8t245 r23 10k r23 10k jp18 signal v select jp18 signal v select a1 3 a2 4 a3 5 a4 6 a5 7 a6 8 a7 9 a8 10 b1 21 b2 20 b3 19 b4 18 b5 17 b6 16 b7 15 b8 14 gnd 11 gnd 12 gnd 13 vcca 1 dir 2 vccb 24 vccb 23 oe 22 u4 74avc8t245 u4 74avc8t245 c45 0.1u c45 0.1u k a d1 hsu119 d1 hsu119 c46 0.1u c46 0.1u c47 0.1u c47 0.1u r24 470 r24 470 c48 0.1u c48 0.1u 1 2 3 4 5 6 7 8 9 10 port3 ctrl port3 ctrl 1 2 3 4 5 6 7 8 9 10 port4 dsp port4 dsp jp20 sdto-in jp20 sdto-in k a led1 erf led1 erf r100 1k r100 1k 2 1 3 sw1 pdn sw1 pdn r26 1k r26 1k c49 0.1u c49 0.1u r27 10k r27 10k jp17 lrck jp17 lrck r28 10k r28 10k r30 1k r30 1k jp21 sdti jp21 sdti jp16 bick jp16 bick 1a 1 1y 2 2a 3 2y 4 3a 5 3y 6 vcc 14 gnd 7 4y 8 4a 9 5y 10 5a 11 6y 12 6a 13 u5 74hc14 u5 74hc14 jp15 mclk jp15 mclk 6 5 4 3 2 1 rp2 47k rp2 47k c50 0.1u c50 0.1u jp19 dir-sel jp19 dir-sel r25 10k r25 10k
5 5 4 4 3 3 2 2 1 1 d d c c b b a a dvdd avdd hvdd tvdd d3v title size document number rev date: sheet of power 1 akd4648-c b 55 friday, march 30, 2007 title size document number rev date: sheet of power 1 akd4648-c b 55 friday, march 30, 2007 title size document number rev date: sheet of power 1 akd4648-c b 55 friday, march 30, 2007 vcc reg agnd agnd c53 0.1u c53 0.1u jp23 tvdd-sel jp23 tvdd-sel r29 10 r29 10 c52 0.1u c52 0.1u 1 agnd1 t45_bk agnd1 t45_bk 1 2 + c55 47u + c55 47u in out gnd t1 ta48033f t1 ta48033f 1 vcc1 t45_red vcc1 t45_red 1 2 + c54 47u + c54 47u 1 dgnd1 t45_bk dgnd1 t45_bk 1 tvdd1 t45_or tvdd1 t45_or 1 2 l2 10u l2 10u 1 2 + c51 47u + c51 47u 1 2 l3 (short) l3 (short) jp22 reg-sel jp22 reg-sel 1 2 l4 (short) l4 (short)
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